on internet april 2013 by zantaz
00000000 1 ; Z8Clk.s
00000000 2 ;
00000000 3 ; Z8 Clock with :
00000000 4 ; a Z86E04 microcontoller (1K)
00000000 5 ; a MK41T56 I2C clock/ram batt bck
00000000 6 ; a 74C925 4 digit counter/multiplx
00000000 7 ; a 4066 for digit control
00000000 8 ; 4 tr BC237, 7805, batt 3V,res
00000000 9 ; 3 key input
00000000 10 ; a buzzer with tr
00000000 11 ;
00000000 12 ; we23jul97 XD. th24jul97 XD.
00000000 13 ; fr25jul97 XD. sa26jul97 XD.
00000000 14 ; su27jul97 XD. mo28jul97 XD.
00000000 15 ; th31jul97 XD. sa 2aug97 XD.
00000000 16 ; su 3aug97 XD. th 7aug97 XD.
00000000 17 ; fr 8aug97 XD. sa 9aug97 XD.
00000000 18 ; su10aug97 XD. su17aug97 XD.
00000000 19 ; th21aug97 XD. fr22aug97 XD.
00000000 20 ; fr 5sep97 XD. mo 8sep97 XD.
00000000 21 ; tu 9sep97 XD. we10sep97 XD.
00000000 22 ;
00000000 23 ; rommed version 1.00
00000000 24 ;
00000000 25 ; rev. 5
00000000 26 ; tc: 8 (*)
00000000 27 ;
00000000 28 ; Z8 pin function
00000000 29 ; P00 (11)o dsp control 3
00000000 30 ; P01 (12)o dsp control 2
00000000 31 ; P02 (13)o dsp control 1
00000000 32 ; dsp 4 always on
00000000 33 ; P20 (15)o clock 74C925
00000000 34 ; P21 (16)o reset 74C925
00000000 35 ; P22 (17)o lth e 74C925
00000000 36 ; P23 (18)io I2C SDA
00000000 37 ; P24 ( 1)o I2C SCL
00000000 38 ; P25 ( 2)o blinking sec led
00000000 39 ; P26 ( 3)o alarm on led
00000000 40 ; P27 ( 4)o buzzer
00000000 41 ; P31 ( 8)i set key active lo
00000000 42 ; P32 ( 9)i minus key act lo
00000000 43 ; P33 (10)i plus key act lo
00000000 44 ;
00000000 45 ;
00000000 46 ; Z8 file reg map
00000000 47 ;
00000000 48 ; 00 01 02 03 04 05 06 07
00000000 49 ; 00H P0 P1 P2 P3 <--- r4-r15
00000000 50 ; 08H work file 00h --->
00000000 51 ; 10H <--- r0-r15
00000000 52 ; 18H work file 10h --->
00000000 53 ; 20H <--- r0-r15
00000000 54 ; 28H work file 20h --->
00000000 55 ; 30H <--- magic pattern ----
00000000 56 ; 38H -stored in Z8 rg file->
00000000 57 ; 40H <----- clock loc ----->
00000000 58 ; 48H alarm afl 0 0 0 0 0
00000000 59 ; 50H <--- magic pattern ----
00000000 60 ; 50H ------ 16 bytes ------>
00000000 61 ; 60H <---- 10 reg of i2c ---
00000000 62 ; 68H rout>
00000000 63 ; 70H <- <- <- <- <- <- <- <-
00000000 64 ; 78H <- <- <- <- <- <- <- sp
00000000 65 ; 00 01 02 03 04 05 06 07
00000000 66 ;
00000000 67 ; general reg assign
00000000 68 ; r0 p0
00000000 69 ; r1 p1
00000000 70 ; r2 p2
00000000 71 ; r3 p3
00000000 72 ; r4 work reg
00000000 73 ; r5
00000000 74 ; r6
00000000 75 ; r7
00000000 76 ; r8
00000000 77 ; r9
00000000 78 ; r10
00000000 79 ; r11
00000000 80 ; r12
00000000 81 ; r13 old_p2m *
00000000 82 ; r14 tcount *
00000000 83 ; r15 tstate *
00000000 84 ;
00000000 85 ; * -> fixed def
00000000 86 ; r0 alias r4
00000000 87 ; r1 alias r5
00000000 88 ; r2 alias r6
00000000 89 ; r3 alias r7
00000000 90 ; r4 alias r8
00000000 91 ; r5 alias r9
00000000 92 ; r6 alias r10
00000000 93 ; r7 alias r11
00000000 94 ; r8
00000000 95 ; r9
00000000 96 ; r10
00000000 97 ; r11
00000000 98 ; r12
00000000 99 ; r13
00000000 100 ; r14 tcount *
00000000 101 ; r15 tstate *
00000000 102 ;
00000000 103 ; work file reg 10h
00000000 104 ;
00000000 105 ;
00000000 106 ; +---------+
00000000 107 ; | EQUATES |
00000000 108 ; +---------+
00000000 109 ;
00000000 110 ;
00000000 111 ; general equates
00000000 112 WORKREG .equ 00H ; wk reg file 00h
00000000 113 MAGICRG .equ 30H ; wk reg file 30h
00000000 114 CLOCKRG .equ 40H ; wk reg file 40h
00000000 115 I2CMREG .equ 50H ; wk reg file 50h
00000000 116 MPATLEN .equ 16
00000000 117 ;
00000000 118 ; display control equates
00000000 119 ; dsp: 123 4 always on
00000000 120 DSP1234 .equ 111B ; normal
00000000 121 DSP134 .equ 101B ; set mode
00000000 122 DSP234 .equ 011B ; hour < 10
00000000 123 DSP124 .equ 110B ; month < 10
00000000 124 DSP24 .equ 010B ; d < 10, m < 10
00000000 125 DSP34 .equ 001B ; only sec
00000000 126 DSP14 .equ 100B ; no prog error
00000000 127 ;
00000000 128 ; i2c clock loc equates
00000000 129 HOUR .equ CLOCKRG+2
00000000 130 MIN .equ CLOCKRG+1
00000000 131 SEC .equ CLOCKRG+0
00000000 132 DAYOW .equ CLOCKRG+3
00000000 133 DAYOM .equ CLOCKRG+4
00000000 134 MONTH .equ CLOCKRG+5
00000000 135 YEAR .equ CLOCKRG+6
00000000 136 CAL .equ CLOCKRG+7
00000000 137 ;
00000000 138 AHOUR .equ CLOCKRG+8
00000000 139 AMIN .equ CLOCKRG+9
00000000 140 ;
00000000 141 ; t0int equates
00000000 142 TCOUNT .equ 1EH ; R14
00000000 143 TSTATE .equ 1FH ; R15
00000000 144 MS250 .equ 250 ; duration in ms
00000000 145 ; of one state
00000000 146 MAXTS .equ 3
00000000 147 TONE .equ 0
00000000 148 TTWO .equ 1
00000000 149 TTHREE .equ 2
00000000 150 TFOUR .equ 3
00000000 151 ;
00000000 152 ; t1int equates
00000000 153 ;
00000000 154 ; chkmpat equates
00000000 155 ;
00000000 156 ; put4bcd equates
00000000 157 ;
00000000 158 ; incdec equates
00000000 159 ;
00000000 160 ; i2c new reg assign
00000000 161 DATA .equ R4
00000000 162 VALUE .equ R5
00000000 163 TEMP .equ R6
00000000 164 BIT_CNT .equ R7
00000000 165 ACK_CNT .equ R8
00000000 166 EE_PTR .equ R9
00000000 167 RAM_PTR .equ R10
00000000 168 DEV_ADDR .equ R11
00000000 169 OLD_P2M .equ R15 ; R13
00000000 170 BYTE_CNT .equ R12
00000000 171 ;
00000000 172 ; i2c routine equates
00000000 173 ;
00000000 174 ; exchange sda with scl
00000000 175 ; fr 5sep97 XD.
00000000 176 ;
00000000 177 ; new old
00000000 178 SDA_HI .EQU #00001000B ; 10H
00000000 179 SDA_LO .EQU #11110111B ; 0EFH
00000000 180 SCLK_HI .EQU #00010000B ; 08H
00000000 181 SCLK_LO .EQU #11101111B ; 0F7H
00000000 182 ;
00000000 183 ; i2c constant
00000000 184 MK41T56 .equ 0D0H
00000000 185 MKSTART .equ 00H
00000000 186 MKLEN .equ 20H
00000000 187 I2CRAM .equ 40H
00000000 188 ;
00000000 189 ; watch dog equ
00000000 190 ; 1 = compile with wdt instr's
00000000 191 WATCHDG .equ 1
00000000 192 ;
00000000 193 ;
00000000 194 ; +--------+
00000000 195 ; | MACROS |
00000000 196 ; +--------+
00000000 197 ;
00000000 198 ;
00000000 199 ; keys macro
00000000 200 TSETK .macro
00000000 201 TM P3,#00000010B ; P31
00000000 202 .endm
00000000 203 TMINUSK .macro
00000000 204 TM P3,#00000100B ; P32
00000000 205 .endm
00000000 206 TPLUSK .macro
00000000 207 TM P3,#00001000B ; P33
00000000 208 .endm
00000000 209 ;
00000000 210 ; put4bcd macros
00000000 211 CLKHI .macro
00000000 212 OR P2,#00000001B ; P20
00000000 213 .endm
00000000 214 CLKLO .macro
00000000 215 AND P2,#11111110B ; P20
00000000 216 .endm
00000000 217 RSTHI .macro
00000000 218 OR P2,#00000010B ; P21
00000000 219 .endm
00000000 220 RSTLO .macro
00000000 221 AND P2,#11111101B ; P21
00000000 222 .endm
00000000 223 MEMHI .macro
00000000 224 OR P2,#00000100B ; P22
00000000 225 .endm
00000000 226 MEMLO .macro
00000000 227 AND P2,#11111011B ; P22
00000000 228 .endm
00000000 229 ;
00000000 230 ; buzzer macro
00000000 231 BUZZER .macro
00000000 232 XOR P2,#10000000B ; P27
00000000 233 .endm
00000000 234 BUZON .macro
00000000 235 OR P2,#10000000B ; P27
00000000 236 .endm
00000000 237 BUZOFF .macro
00000000 238 AND P2,#01111111B ; P27
00000000 239 .endm
00000000 240 ;
00000000 241 ; alarm macros
00000000 242 ALMON .macro
00000000 243 AND P2,#10111111B ; P26
00000000 244 .endm
00000000 245 ALMOFF .macro
00000000 246 OR P2,#01000000B ; P26
00000000 247 .endm
00000000 248 TALM .macro
00000000 249 TCM P2,#01000000B ; P26
00000000 250 .endm
00000000 251 ;
00000000 252 ; blink sec macros
00000000 253 SECON .macro
00000000 254 AND P2,#11011111B ; P25
00000000 255 .endm
00000000 256 SECOFF .macro
00000000 257 OR P2,#00100000B ; P25
00000000 258 .endm
00000000 259 ;
00000000 260 ; watch dog macro
00000000 261 WDOG .macro
00000000 262 .if WATCHDG
00000000 263 .byte 5FH ; WDT
00000000 264 .endif
00000000 265 .endm
00000000 266 ;
00000000 267 ;
00000000 268 ; +---------------+
00000000 269 ; | START OTP ROM |
00000000 270 ; +---------------+
00000000 271 ;
00000000 272 ;
00000000 273 .org 0000H
00000000 01ba 274 .word P3INT
00000002 01ba 275 .word P3INT
00000004 01ba 276 .word P3INT
00000006 000c 277 .word RESET ; ?
00000008 01c7 278 .word T0INT
0000000a 020c 279 .word T1INT
0000000c 280 ;
0000000c 281 .org 000CH
0000000c 8f 282 RESET DI
0000000d 283 ; P00-P02 out stack internal
0000000d 284 ; LD P0,#00000010B
0000000d e6f804 285 LD P01M,#00000100B
00000010 286 ; all P2 pin are output
00000010 287 ; LD OLD_P2M,#00000000B
00000010 b0ef 288 CLR OLD_P2M
00000012 f9f6 289 LD P2M,OLD_P2M
00000014 290 ; buz=0 alm=1 sec=1
00000014 291 ; scl=1 sda=1
00000014 292 ; mem=0 (1?) rst=0 (1?) clk=0
00000014 e60278 293 LD P2,#01111000B
00000017 294 ; LD P2,#01111110B
00000017 295 ; P31-P33 digital input
00000017 e6f701 296 LD P3M,#01H
0000001a 297 ; init stack pointer
0000001a b0fe 298 CLR SPH
0000001c e6ff80 299 LD SPL,#80H
0000001f 300 ; store in ram magic pattern
0000001f 301 ; and switch to workreg
0000001f d60210 302 CALL STOMPAT
00000022 303 ; SRP #WORKREG
00000022 304 ; irq4 max pri -> irq5 -> ...
00000022 e6f903 305 LD IPR,#3
00000025 306 ; enable irq4
00000025 e6fb10 307 LD IMR,#00010000B
00000028 308 ; enbl irq5 irq4 irq2 irq1 irq0
00000028 309 ; LD IMR,#00110111B
00000028 310 ; LD IMR,#00110000B
00000028 311 ; clear irq request
00000028 b0fa 312 CLR IRQ
0000002a 313 ; pre div50 modulo n
0000002a e6f5c9 314 LD PRE0,#11001001B
0000002d e6f414 315 LD T0,#20 ; 1 ms
00000030 316 ; init timer var
00000030 b01e 317 CLR TCOUNT
00000032 b01f 318 CLR TSTATE
00000034 319 ; load enbl t0
00000034 e6f103 320 LD TMR,#3
00000037 321 ;
00000037 322 ; the alarm is coded in this way:
00000037 323 ; the two timer and the P3 int
00000037 324 ; are enabled when alarm time is
00000037 325 ; equal the actual time
00000037 326 ; when a key is pressed the int
00000037 327 ; are disabled
00000037 328 ;
00000037 329 ;
00000037 330 ; +--------------+
00000037 331 ; | MAIN PROGRAM |
00000037 332 ; +--------------+
00000037 333 ;
00000037 334 ; enable interrupt
00000037 9f 335 BEGIN EI
00000038 5f 336 WDOG
00000039 337 ; wait 250 ms for 1 ms time slot
00000039 441e1e 338 OR TCOUNT,TCOUNT ; = 0
0000003c ebf9 339 JR NZ,BEGIN
0000003e 340 ;
0000003e 341 ; get clock data from i2c mk41t56
0000003e 342 ;
0000003e bcd0 343 LD DEV_ADDR,#MK41T56
00000040 9c00 344 LD EE_PTR,#MKSTART
00000042 ac40 345 LD RAM_PTR,#I2CRAM
00000044 cc20 346 LD BYTE_CNT,#MKLEN
00000046 d6030c 347 CALL PG_RD
00000049 348 ;
00000049 349 ; check the i2c read if it's len
00000049 350 ; is high than 1 ms (20 byte)
00000049 351 ; or
00000049 352 ; insert delay here for one read
00000049 353 ; on every 250 ms
00000049 354 ;
00000049 355 ; CALL KDEL
00000049 356 ;
00000049 357 ; test for setup key
00000049 760302 358 STRT TSETK ; 'set' key
0000004c 6b76 359 JR Z,SETUP
0000004e 360 ;
0000004e 361 ; check if mk pattern match
0000004e 362 ; if yes continue
0000004e 363 ; if no blink 9999 and 9--9
0000004e 364 ;
0000004e d60235 365 CALL CHKMPAT
00000051 7b11 366 JR C,STR0
00000053 367 ;
00000053 368 ; display 9-blank-blank-9 and
00000053 369 ; 9-9-9-9
00000053 370 ;
00000053 371 ; LD R5,#99H
00000053 372 ; LD R6,#99H
00000053 373 ; CALL PUT4BCD
00000053 d60249 374 CALL PUT9999
00000056 375 ; display 9-blank-blank-9
00000056 e60004 376 LD P0,#DSP14
00000059 d602e4 377 CALL SDEL
0000005c 378 ; display 9-9-9-9
0000005c e60007 379 LD P0,#DSP1234
0000005f d602e4 380 CALL SDEL
00000062 381 ;
00000062 8bd3 382 JR BEGIN
00000064 383 ;
00000064 384 ; check if alarm flag is on
00000064 660240 385 STR0 TALM
00000067 6b17 386 JR Z,STR1
00000069 387 ; check if is alarm time
00000069 a44842 388 CP HOUR,AHOUR
0000006c eb12 389 JR NZ,STR1
0000006e a44941 390 CP MIN,AMIN
00000071 eb0d 391 JR NZ,STR1
00000073 392 ; OR SEC,SEC
00000073 a64000 393 CP SEC,#0
00000076 eb08 394 JR NZ,STR1
00000078 395 ;
00000078 396 ; alarm time has been reached
00000078 397 ;
00000078 8f 398 DI
00000079 399 ; load enable t1 really need ?
00000079 400 ; OR TMR,#0CH
00000079 401 ; enable irq5 irq4 irq2 irq1 irq0
00000079 46fb37 402 OR IMR,#00110111B
0000007c 403 ; disable irq2 irq1 irq0
0000007c 56faf8 404 AND IRQ,#11111000B
0000007f 405 ; or CLR IRQ
0000007f 9f 406 EI ; enable interrupt
00000080 407 ;
00000080 760304 408 STR1 TMINUSK ; '-' key
00000083 6b1b 409 JR Z,DSPDM
00000085 410 ;
00000085 760308 411 TPLUSK ; '+' key
00000088 6b30 412 JR Z,DSPAL
0000008a 413 ;
0000008a 414 ; show hour & min
0000008a 415 ;
0000008a 5842 416 LD R5,HOUR
0000008c 6841 417 LD R6,MIN
0000008e d6024f 418 CALL PUT4B1
00000091 419 ;
00000091 420 ; sec blinking led
00000091 421 ;
00000091 764001 422 TM SEC,#1
00000094 eb05 423 JR NZ,SEC0
00000096 460220 424 SECOFF
00000099 8b03 425 JR STR2
0000009b 5602df 426 SEC0 SECON
0000009e 427 ;
0000009e 8b97 428 STR2 JR BEGIN
000000a0 429 ;
000000a0 430 ; show dayom & month
000000a0 431 ;
000000a0 760308 432 DSPDM TPLUSK
000000a3 eb0b 433 JR NZ,DSPDM0
000000a5 434 ;
000000a5 435 ; LD R5,DAYOW
000000a5 436 ; LD R6,YEAR
000000a5 437 ; CALL PUT4B1
000000a5 dc01 438 LD R13,#DSP34
000000a7 439 ;
000000a7 b0e5 440 CLR R5
000000a9 6840 441 LD R6,SEC
000000ab d6026c 442 CALL PUT4BCD
000000ae 443 ;
000000ae 8b87 444 JR BEGIN
000000b0 445 ;
000000b0 5844 446 DSPDM0 LD R5,DAYOM
000000b2 6845 447 LD R6,MONTH
000000b4 d6025a 448 CALL PUT4B2
000000b7 449 ;
000000b7 8d0037 450 JP BEGIN
000000ba 451 ;
000000ba 452 ; show alarm time
000000ba 453 ;
000000ba 5848 454 DSPAL LD R5,AHOUR
000000bc 6849 455 LD R6,AMIN
000000be d6024f 456 CALL PUT4B1
000000c1 457 ;
000000c1 8d0037 458 JP BEGIN
000000c4 459 ;
000000c4 460 ;
000000c4 461 ; +------------+
000000c4 462 ; | SETUP CODE |
000000c4 463 ; +------------+
000000c4 464 ;
000000c4 465 ;
000000c4 466 ; when entered the setup mode
000000c4 467 ; with key press of set key
000000c4 468 ; -> minus key enter the clock
000000c4 469 ; setup mode
000000c4 470 ; -> plus key enter the alarm
000000c4 471 ; time mode
000000c4 472 ; the display show: 0-blank-0-0
000000c4 473 ;
000000c4 474 ; setup code
000000c4 475 ;
000000c4 476 ; include a simple password:
000000c4 477 ; - press setup
000000c4 478 ; - press plus
000000c4 479 ; - press minus
000000c4 480 ; -> enter setup code
000000c4 481 ; with time out on key
000000c4 482 ; when time out is reached
000000c4 483 ; back to main loop (START)
000000c4 484 ;
000000c4 485 ; control if there is a pattern
000000c4 486 ; in user ram of mk41t56
000000c4 487 ; pattern stored on loc.
000000c4 488 ; 08H -> 0FH len: 8
000000c4 489 ; if yes read mk clock data
000000c4 490 ; if no fill clock data with 0
000000c4 491 ;
000000c4 492 ; read mk41t56 data on 50H-5FH
000000c4 493 ;
000000c4 494 SETUP
000000c4 495 ; this code is already made
000000c4 496 ; LD DEV_ADDR,MK41T56
000000c4 497 ; LD EE_PTR,#MKSTART
000000c4 498 ; LD RAM_PTR,#I2CRAM
000000c4 499 ; LD BYTE_CNT,#MKLEN
000000c4 500 ; CALL PG_RD
000000c4 501 ;
000000c4 502 ; check if mk pattern match
000000c4 503 ; if yes normal setup
000000c4 504 ; if no clear clock data setup
000000c4 505 ;
000000c4 d60235 506 CALL CHKMPAT
000000c7 7b09 507 JR C,SETC0
000000c9 508 ; no pattern found -> clear loc
000000c9 509 ; clear clock data on ram
000000c9 510 ;
000000c9 511 ; r4 index reg
000000c9 512 ; r5 count reg
000000c9 513 ;
000000c9 4c40 514 LD R4,#CLOCKRG
000000cb 5c20 515 LD R5,#MKLEN ; 32 ram loc
000000cd b1e4 516 CLP0 CLR @R4
000000cf 4e 517 INC R4
000000d0 5afb 518 DJNZ R5,CLP0
000000d2 519 ;
000000d2 520
000000d2 521 ;
000000d2 522 ; 0-blank-0-0 -> wait minus (clock)
000000d2 523 ; or plus (alarm)
000000d2 524 ; key and enter mode
000000d2 525 ;
000000d2 526 ; 1-blank-X-X -> set hour
000000d2 527 ; 2-blank-X-X -> set min
000000d2 528 ; 3-blank-X-X -> set dayow
000000d2 529 ; 4-blank-X-X -> set dayom
000000d2 530 ; 5-blank-X-X -> set month
000000d2 531 ; 6-blank-X-X -> set year
000000d2 532 ; 7-blank-X-X -> set cal
000000d2 533 ; 9-blank-9-9 -> wait set key
000000d2 534 ; to start time
000000d2 535 ;
000000d2 536 ; 1-blank-X-X -> set alarm hour
000000d2 537 ; 2-blank-X-X -> set alarm min
000000d2 538 ; 9-blank-9-9 -> on/off alarm &
000000d2 539 ; wait set key
000000d2 540 ; off alarm with minus key
000000d2 541 ; on alarm with plus key
000000d2 542 ;
000000d2 543
000000d2 544
000000d2 5f 545 SETC0 WDOG
000000d3 760302 546 TSETK ; wait set key release
000000d6 6bfa 547 JR Z,SETC0
000000d8 548 ;
000000d8 dc05 549 LD R13,#DSP134 ; set mode d
000000da b0e5 550 CLR R5
000000dc b0e6 551 CLR R6
000000de d6026c 552 CALL PUT4BCD
000000e1 553 ;
000000e1 cc0a 554 LD R12,#10
000000e3 555 ;
000000e3 5f 556 STC1 WDOG
000000e4 760304 557 TMINUSK
000000e7 6b4e 558 JR Z,SETCLK
000000e9 559 ;
000000e9 760308 560 TPLUSK
000000ec 6b08 561 JR Z,SETALM
000000ee 562 ;
000000ee 760302 563 TSETK
000000f1 6d0037 564 JP Z,BEGIN
000000f4 565 ;
000000f4 8bed 566 JR STC1 ; back again
000000f6 567 ;
000000f6 568 ; setup alarm time
000000f6 569 ;
000000f6 5f 570 SETALM WDOG
000000f7 760308 571 TPLUSK ; wait key release
000000fa 6bfa 572 JR Z,SETALM
000000fc 573 ;
000000fc 574 STA0 ; LD R12,#10H ; 1000 set num
000000fc 575 ;point to clock alarm hour loc
000000fc 7c48 576 LD R7,#AHOUR
000000fe 577 ;
000000fe 8c23 578 LD R8,#23H ; set alarm hour
00000100 9c00 579 LD R9,#00H
00000102 d602a6 580 CALL INCDEC
00000105 581 ;
00000105 582 ; LD R7,AMIN ; set alarm min
00000105 8c59 583 LD R8,#59H
00000107 584 ; LD R7,#00H
00000107 d602a6 585 CALL INCDEC
0000010a 586 ;
0000010a 587 ; end setup sequence
0000010a 588 ; signal with 9-blank-99
0000010a 589 ;
0000010a 590 ; LD R5,#90H
0000010a 591 ; LD R6,#99H
0000010a 592 ; CALL PUT4BCD
0000010a d60249 593 CALL PUT9999
0000010d 594 ;
0000010d 595 ; on/off alarm wait set key
0000010d 596 ; check on alarm key
0000010d 5f 597 SA0 WDOG
0000010e 760308 598 TPLUSK
00000111 eb03 599 JR NZ,SA1
00000113 600 ; turn on alarm led
00000113 5602bf 601 ALMON
00000116 602 ;
00000116 603 ; check off alarm key
00000116 760304 604 SA1 TMINUSK
00000119 eb03 605 JR NZ,SA2
0000011b 606 ; turn off alarm led
0000011b 460240 607 ALMOFF
0000011e 608 ;
0000011e 609 ; check set key
0000011e 760302 610 SA2 TSETK
00000121 ebea 611 JR NZ,SA0
00000123 612 ; wait release of set key
00000123 5f 613 SA3 WDOG
00000124 760302 614 TSETK
00000127 6bfa 615 JR Z,SA3
00000129 616 ;
00000129 617 ; put data to i2c mk41t56
00000129 618 ; address 48H -> 49H len: 2
00000129 619 ;
00000129 bcd0 620 LD DEV_ADDR,#MK41T56
0000012b 9c08 621 LD EE_PTR,#MKSTART+8
0000012d ac48 622 LD RAM_PTR,#I2CRAM+8
0000012f cc02 623 LD BYTE_CNT,#2
00000131 d602ee 624 CALL PG_WR
00000134 625 ;
00000134 8d0037 626 JP BEGIN
00000137 627 ;
00000137 628 ; setup clock location
00000137 629 ;
00000137 5f 630 SETCLK WDOG
00000138 760304 631 TMINUSK ; wait key release
0000013b 6bfa 632 JR Z,SETCLK
0000013d 633 ;
0000013d 634 ; start setup sequence
0000013d 635 ; r5 = 10h start set num
0000013d 636 ; r7 = 40h start clock loc
0000013d 637 ;
0000013d 638 SET0 ; LD R12,#10H ; 1000 set num
0000013d 639 ;point to clock hour loc
0000013d 7c42 640 LD R7,#HOUR
0000013f 641 ;
0000013f 8c23 642 LD R8,#23H ; set hour
00000141 9c00 643 LD R9,#00H
00000143 d602a6 644 CALL INCDEC
00000146 645 ;
00000146 7c41 646 LD R7,#MIN ; set min
00000148 8c59 647 LD R8,#59H
0000014a 648 ; LD R7,#00H
0000014a d602a6 649 CALL INCDEC
0000014d 650 ;
0000014d 7c43 651 LD R7,#DAYOW ; set dayow
0000014f 8c07 652 LD R8,#07H
00000151 9c01 653 LD R9,#01H
00000153 d602a6 654 CALL INCDEC
00000156 655 ;
00000156 656 ; LD R5,#DAYOM ; set dayom
00000156 8c31 657 LD R8,#31H
00000158 658 ; LD R7,#01H
00000158 d602a6 659 CALL INCDEC
0000015b 660 ;
0000015b 661 ; LD R7,#MONTH ; set month
0000015b 8c12 662 LD R8,#12H
0000015d 663 ; LD R9,#01H
0000015d d602a6 664 CALL INCDEC
00000160 665 ;
00000160 666 ; LD R7,#YEAR ; set year
00000160 8c99 667 LD R8,#99H
00000162 9c00 668 LD R9,#00H
00000164 d602a6 669 CALL INCDEC
00000167 670 ;
00000167 671 ; now must convert cal from
00000167 672 ; bin to bcd
00000167 673 ;
00000167 674 ; r5 work reg
00000167 675 ;
00000167 5847 676 BINTBCD LD R5,CAL ; fetch cal
00000169 b047 677 CLR CAL ; clear cal
0000016b 678 ; CP R5,#0 ; if cal = 0
0000016b 5255 679 AND R5,R5
0000016d 6b07 680 JR Z,BB4 ; jump
0000016f 064701 681 BB5 ADD CAL,#1 ; add 1
00000172 4047 682 DA CAL ; dec adjust
00000174 5af9 683 DJNZ R5,BB5 ; do again
00000176 684 BB4
00000176 685 ;
00000176 686 ; maybe the istruction CP R5,#0 can
00000176 687 ; be replaced by OR R5,R5
00000176 688 ; 3 byte vs. 2 byte
00000176 689 ; work only with working reg
00000176 690 ;
00000176 691 ; LD R7,#CAL ; set cal
00000176 8c63 692 LD R8,#63H
00000178 693 ; LD R9,#00H
00000178 d602a6 694 CALL INCDEC
0000017b 695 ;
0000017b 696 ; the loc 47H (cal) is in bcd
0000017b 697 ; convert to 5+1 bit binary
0000017b 698 ; and the output bit ?
0000017b 699 ;
0000017b 700 ; r5 tenth value of cal
0000017b 701 ; r6 unit value of cal
0000017b 702 ; r7 bcd to binary value conv
0000017b 703 ;
0000017b 5847 704 BCDTBIN LD R5,CAL ; fetch cal
0000017d 68e5 705 LD R6,R5 ; copy it
0000017f 56e60f 706 AND R6,#0FH ; mask lo nibl
00000182 f0e5 707 SWAP R5 ; swap nibble
00000184 56e50f 708 AND R5,#0FH ; mask lo nibl
00000187 b0e7 709 CLR R7 ; clr bin reg
00000189 710 ; CP R5,#0 ; tenth = 0
00000189 5255 711 AND R5,R5
0000018b 6b05 712 JR Z,BB1 ; jump over
0000018d 06e70a 713 BB0 ADD R7,#10 ; add 10 to bin
00000190 5afb 714 DJNZ R5,BB0 ; again
00000192 0276 715 BB1 ADD R7,R6 ; add unit to b
00000194 7947 716 LD CAL,R7 ; store new cal
00000196 717 ;
00000196 718 ; end setup sequence
00000196 719 ; signal with 9-blank-99
00000196 720 ;
00000196 721 ; LD R5,#90H
00000196 722 ; LD R6,#99H
00000196 723 ; CALL PUT4BCD
00000196 d60249 724 CALL PUT9999
00000199 725 ;
00000199 726 ; wait set key
00000199 5f 727 WAITK WDOG
0000019a 760302 728 TSETK ; 'set' key
0000019d ebfa 729 JR NZ,WAITK
0000019f 730 ;
0000019f 5f 731 WAITK2 WDOG
000001a0 760302 732 TSETK ; 'set' key
000001a3 6bfa 733 JR Z,WAITK2
000001a5 734 ;
000001a5 b040 735 CLR SEC ; clear sec
000001a7 736 ;
000001a7 737 ; copy pattern in ram
000001a7 738 ;
000001a7 3150 739 SRP #I2CMREG
000001a9 d60212 740 CALL STOMRAM
000001ac 741 ;
000001ac 742 ; store data in mk41t56
000001ac 743 ;
000001ac 744 ; put data to i2c mk41t56
000001ac 745 ; address 40H -> 5FH len: 32
000001ac 746 ;
000001ac bcd0 747 LD DEV_ADDR,#MK41T56
000001ae 9c00 748 LD EE_PTR,#MKSTART
000001b0 ac40 749 LD RAM_PTR,#I2CRAM
000001b2 cc20 750 LD BYTE_CNT,#MKLEN
000001b4 d602ee 751 CALL PG_WR
000001b7 752 ;
000001b7 8d0037 753 JP BEGIN ; back again
000001ba 754 ;
000001ba 755 ;
000001ba 756 ; +--------------------+
000001ba 757 ; | INTERRUPT ROUTINES |
000001ba 758 ; +--------------------+
000001ba 759 ;
000001ba 760 ;
000001ba 761 ; use of falling edge interrupt
000001ba 762 ; on P31, P32, P33
000001ba 763 ; when interrupt are enabled
000001ba 764 ; for alarm time buzzer that can
000001ba 765 ; stopped it
000001ba 766 ;
000001ba 460240 767 P3INT ALMOFF
000001bd 768 ;
000001bd 769 ; wait key release
000001bd 5f 770 STB WDOG
000001be 66030e 771 TCM P3,#00001110B
000001c1 ebfa 772 JR NZ,STB
000001c3 773 ; enable irq4 only
000001c3 56fb10 774 AND IMR,#00010000B
000001c6 775 ; reset o set buzzer now ?
000001c6 bf 776 IRET
000001c7 777 ;
000001c7 778 ; 1 ms timer routine
000001c7 779 ;
000001c7 201e 780 T0INT INC TCOUNT
000001c9 a61efa 781 CP TCOUNT,#MS250
000001cc eb3d 782 JR NE,TI1
000001ce 783 ; 250 ms section
000001ce a61f00 784 ST1 CP TSTATE,#TONE
000001d1 eb09 785 JR NE,ST2
000001d3 786 ; pre1 div4 modulo n
000001d3 e6f313 787 LD PRE1,#00010011B
000001d6 e6f2f0 788 LD T1,#0F0H ;
000001d9 789 ; load enbl t1
000001d9 46f10c 790 OR TMR,#0CH
000001dc 791 ;
000001dc a61f01 792 ST2 CP TSTATE,#TTWO
000001df eb09 793 JR NE,ST3
000001e1 794 ; pre1 div4 modulo n
000001e1 e6f313 795 LD PRE1,#00010011B
000001e4 e6f265 796 LD T1,#65H ;
000001e7 797 ; load enbl t1
000001e7 46f10c 798 OR TMR,#0CH
000001ea 799 ;
000001ea a61f02 800 ST3 CP TSTATE,#TTHREE
000001ed eb09 801 JR NE,ST4
000001ef 802 ; pre1 div4 modulo n
000001ef e6f313 803 LD PRE1,#00010011B
000001f2 e6f2a0 804 LD T1,#0A0H ;
000001f5 805 ; load enbl t1
000001f5 46f10c 806 OR TMR,#0CH
000001f8 807 ;
000001f8 a61f03 808 ST4 CP TSTATE,#TFOUR
000001fb eb03 809 JR NE,ST5
000001fd 810 ; no load no enbl t1
000001fd 56f1f3 811 AND TMR,#11110011B
00000200 812 ;
00000200 201f 813 ST5 INC TSTATE
00000202 a61f03 814 CP TSTATE,#MAXTS
00000205 3b02 815 JR ULE,TI0
00000207 b01f 816 CLR TSTATE
00000209 817 ;
00000209 b01e 818 TI0 CLR TCOUNT
0000020b bf 819 TI1 IRET
0000020c 820 ;
0000020c 821
0000020c 822 ; change the state of buzzer pin
0000020c 823 ;
0000020c b60280 824 T1INT BUZZER ; toggle buzzer bit
0000020f 825 ;
0000020f bf 826 IRET
00000210 827 ;
00000210 828 ;
00000210 829 ; +-------------+
00000210 830 ; | SUBROUTINES |
00000210 831 ; +-------------+
00000210 832 ;
00000210 833 ; store in wk reg file magic patrn
00000210 834 ; for use of rom protection option
00000210 835 ; "Z8Clk by XD.97" len: 14
00000210 836 ; "Z8Clock by XD.97" len: 16
00000210 837 ; "Z8Clk by XD. '97" len: 16
00000210 838 ; "Z8Clk by XD.1997" len: 16
00000210 839 ;
00000210 3130 840 STOMPAT SRP #MAGICRG
00000212 841 ;
00000212 0c5a 842 STOMRAM LD R0, #'Z'
00000214 1c38 843 LD R1, #'8'
00000216 2c43 844 LD R2, #'C'
00000218 3c6c 845 LD R3, #'l'
0000021a 4c6b 846 LD R4, #'k'
0000021c 5c20 847 LD R5, #' '
0000021e 6c62 848 LD R6, #'b'
00000220 7c79 849 LD R7, #'y'
00000222 8c20 850 LD R8, #' '
00000224 9c58 851 LD R9, #'X'
00000226 ac44 852 LD R10,#'D'
00000228 bc2e 853 LD R11,#'.'
0000022a cc31 854 LD R12,#'1'
0000022c dc39 855 LD R13,#'9'
0000022e ec39 856 LD R14,#'9'
00000230 fc37 857 LD R15,#'7'
00000232 858 ;
00000232 3100 859 SRP #WORKREG
00000234 860 ;
00000234 af 861 RET
00000235 862 ;
00000235 863 ; check magic pattern routine
00000235 864 ;
00000235 865 ; r4 work reg
00000235 866 ; r5 counter reg
00000235 867 ; r6 index to i2c loc in ram
00000235 868 ; r7 index to magic pat in ram
00000235 869 ;
00000235 870 ; on exit:
00000235 871 ; carry flag on: pattern match
00000235 872 ; carry flag off: pattern don't m
00000235 873 ;
00000235 874 CHKMPAT
00000235 875 ; this code already made
00000235 876 ; CALL STOMPAT
00000235 877 ;
00000235 5c10 878 LD R5,#MPATLEN
00000237 6c50 879 LD R6,#I2CMREG
00000239 7c30 880 LD R7,#MAGICRG
0000023b e346 881 CK0 LD R4,@R6
0000023d a347 882 CP R4,@R7
0000023f eb06 883 JR NZ,ERRMPAT
00000241 6e 884 INC R6
00000242 7e 885 INC R7
00000243 5af6 886 DJNZ R5,CK0
00000245 df 887 SCF
00000246 af 888 RET
00000247 889 ;
00000247 cf 890 ERRMPAT RCF
00000248 af 891 RET
00000249 892 ;
00000249 893
00000249 894 ;
00000249 895 ; put 9999 on display routine
00000249 896 ; usd: r4,r5,r6
00000249 897 ; flows in put4bcd
00000249 898 ;
00000249 5c99 899 PUT9999 LD R5,#99H
0000024b 6c99 900 LD R6,#99H
0000024d 901 ;
0000024d 8b1d 902 JR PUT4BCD
0000024f 903 ;
0000024f 904 ; put 4 bcd version 1
0000024f 905 ; blank dsp1 if hi nibble of r5
0000024f 906 ; is '0'
0000024f 907 ;
0000024f dc07 908 PUT4B1 LD R13,#DSP1234
00000251 909 ;
00000251 76e5f0 910 TM R5,#11110000B
00000254 eb02 911 JR NZ,PB0
00000256 912 ;
00000256 dc03 913 LD R13,#DSP234
00000258 914 ;
00000258 8b12 915 PB0 JR PUT4BCD
0000025a 916 ;
0000025a 917 ; put 4 bcd version 2
0000025a 918 ; blank dsp1 if hi nibble of r5
0000025a 919 ; is '0', blank dsp3 if hi nibble
0000025a 920 ; of r6 is '0'
0000025a 921 ;
0000025a dc07 922 PUT4B2 LD R13,#DSP1234
0000025c 923 ;
0000025c 76e5f0 924 TM R5,#11110000B
0000025f eb03 925 JR NZ,PB1
00000261 926 ;
00000261 56ed03 927 AND R13,#DSP234
00000264 928 ;
00000264 76e6f0 929 PB1 TM R6,#11110000B
00000267 eb03 930 JR NZ,PB2
00000269 931 ;
00000269 56ed06 932 AND R13,#DSP124
0000026c 933 ;
0000026c 934 PB2 ; JR PUT4BCD
0000026c 935 ;
0000026c 936 ; put 4 bcd number on 74C925 dsp
0000026c 937 ; output value on 74C925 displays
0000026c 938 ; 74C925 is scaled version of C926
0000026c 939 ;
0000026c 940 ; r4 work reg
0000026c 941 ; r5 hi 2 bcd number
0000026c 942 ; r6 lo 2 bcd number
0000026c 943 ; r13 port 0 new value
0000026c 944 ;
0000026c 945 ; turn sec led off
0000026c 5f 946 PUT4BCD WDOG
0000026d 947 ;
0000026d 948 ; SECOFF
0000026d 949 ;
0000026d 460202 950 RSTHI ; reset C925
00000270 5602fd 951 RSTLO ; reset off
00000273 952 ;
00000273 4255 953 OR R5,R5
00000275 954 ; CP R5,#0
00000275 6b12 955 JR Z,OV0
00000277 956 ;
00000277 4c64 957 OUT1 LD R4,#100
00000279 958 ;
00000279 460201 959 OUT12 CLKHI ; one count
0000027c 5602fe 960 CLKLO
0000027f 961 ;
0000027f 5f 962 WDOG ; * (for long count)
00000280 963 ;
00000280 4af7 964 DJNZ R4,OUT12
00000282 965 ;
00000282 26e501 966 SUB R5,#1
00000285 40e5 967 DA R5
00000287 ebee 968 JR NZ,OUT1
00000289 969 ;
00000289 4266 970 OV0 OR R6,R6
0000028b 971 ; CP R6,#0
0000028b 6b0d 972 JR Z,OV1
0000028d 973 ;
0000028d 460201 974 OUT2 CLKHI ; one count
00000290 5602fe 975 CLKLO
00000293 976 ;
00000293 26e601 977 SUB R6,#1
00000296 40e6 978 DA R6
00000298 ebf3 979 JR NZ,OUT2
0000029a 980 ;
0000029a 460204 981 OV1 MEMHI ; mem off
0000029d 5602fb 982 MEMLO ; mem on
000002a0 983 ;
000002a0 460220 984 SECOFF
000002a3 985 ;
000002a3 d900 986 LD P0,R13
000002a5 987 ;
000002a5 af 988 RET
000002a6 989 ;
000002a6 990 ; inc dec routine
000002a6 991 ; on entry:
000002a6 992 ;
000002a6 993 ; r5 set number (10h,20h,..,90h)
000002a6 994 ; r7 point to incdec loc
000002a6 995 ; that point to bcd coded loc
000002a6 996 ; r8 hi limit bcd coded
000002a6 997 ; r9 lo limit " "
000002a6 998 ;
000002a6 999 ; out:
000002a6 1000 ; r5 = r5 + 10h
000002a6 1001 ; r7 = r7 + 1
000002a6 1002 ;
000002a6 1003 ; usd:
000002a6 1004 ; r4 work reg
000002a6 1005 ; r5 put4bcd hi 2 bcd
000002a6 1006 ; r6 put4bcd lo 2 bcd
000002a6 1007 ; r7 point to incdec loc bcd coded
000002a6 1008 ; r8 hi limit bcd coded
000002a6 1009 ; r9 lo limit " "
000002a6 1010 ; r10 delay reg hi
000002a6 1011 ; r11 delay reg lo
000002a6 1012 ; r12 hi bcd save reg
000002a6 1013 ;
000002a6 1014 ; port bit -> key assign
000002a6 1015 ; P31 set key
000002a6 1016 ; P32 minus key
000002a6 1017 ; P33 plus key
000002a6 1018 ;
000002a6 1019 ;
000002a6 760308 1020 INCDEC TPLUSK ; '+' key
000002a9 eb0d 1021 JR NZ,IN0
000002ab a387 1022 CP R8,@R7
000002ad bb04 1023 JR UGT,IN3
000002af f379 1024 LD @R7,R9
000002b1 8b05 1025 JR IN0
000002b3 07e701 1026 IN3 ADD @R7,#1
000002b6 41e7 1027 DA @R7
000002b8 760304 1028 IN0 TMINUSK ; '-' key
000002bb eb0d 1029 JR NZ,IN1
000002bd a397 1030 CP R9,@R7
000002bf 7b04 1031 JR ULT,IN4
000002c1 f378 1032 LD @R7,R8
000002c3 8b05 1033 JR IN1
000002c5 27e701 1034 IN4 SUB @R7,#1
000002c8 41e7 1035 DA @R7
000002ca e367 1036 IN1 LD R6,@R7
000002cc 1037 ; r5 hi2bcd r6 lo2bcd
000002cc 58ec 1038 LD R5,R12
000002ce d6026c 1039 CALL PUT4BCD
000002d1 d602e4 1040 CALL KDEL
000002d4 760302 1041 TSETK ; 'set' k
000002d7 ebcd 1042 JR NZ,INCDEC
000002d9 5f 1043 IN5 WDOG
000002da 760302 1044 TSETK ; 'set' k rel
000002dd 6bfa 1045 JR Z,IN5
000002df 1046 ; do the incs
000002df 06ec10 1047 ADD R12,#10H
000002e2 7e 1048 INC R7
000002e3 af 1049 RET
000002e4 1050 ;
000002e4 1051 ; key delay routine
000002e4 1052 ;
000002e4 1053 ; r10 hi delay reg
000002e4 1054 ; r11 lo delay reg
000002e4 1055 ;
000002e4 1056 KDEL ; LD R10,#97H ; 0A0H ; 65H
000002e4 1057 ; JR SD0
000002e4 1058 ;
000002e4 1059 ; setnum delay routine
000002e4 1060 ;
000002e4 1061 ; r10 hi delay reg
000002e4 1062 ; r11 lo delay reg
000002e4 1063 ;
000002e4 ac80 1064 SDEL LD R10,#80H
000002e6 1065 ; LD R10,#0
000002e6 1066 ;
000002e6 b0eb 1067 SK0 CLR R11
000002e8 1068 ; LD R10,#0
000002e8 5f 1069 SD0 WDOG ; check istr time
000002e9 80ea 1070 DECW RR10
000002eb ebfb 1071 JR NZ,SD0
000002ed af 1072 RET
000002ee 1073 ;
000002ee 1074 ;
000002ee 1075 ; +-----------------+
000002ee 1076 ; | I2C SUBROUTINES |
000002ee 1077 ; +-----------------+
000002ee 1078 ;
000002ee 1079 ;
000002ee 1080 ; pg_wr routine
000002ee 1081 ; write byte_cnt to i2c device
000002ee 1082 ;
000002ee d6037a 1083 PG_WR CALL WR_POLL
000002f1 48e9 1084 LD DATA, EE_PTR
000002f3 d60354 1085 CALL OUTBYT
000002f6 d60369 1086 CALL REC_ACK
000002f9 1087 ; JP C, E_ERR
000002f9 7bfe 1088 EE0 JR C,EE0 ; freeze for error
000002fb e34a 1089 PG_WR1 LD DATA,@RAM_PTR
000002fd d60354 1090 CALL OUTBYT
00000300 d60369 1091 CALL REC_ACK
00000303 1092 ; JP C, EE_ERR
00000303 7bfe 1093 EE1 JR C,EE1 ; freeze for error
00000305 ae 1094 INC RAM_PTR
00000306 caf3 1095 DJNZ BYTE_CNT,PG_WR1
00000308 d603a4 1096 CALL STOP
0000030b af 1097 RET
0000030c 1098 ;
0000030c 1099 ; pg_rd routine
0000030c 1100 ; read byte_cnt from i2c device
0000030c 1101 ;
0000030c d6037a 1102 PG_RD CALL WR_POLL
0000030f 48e9 1103 LD DATA,EE_PTR
00000311 d60354 1104 CALL OUTBYT
00000314 d60369 1105 CALL REC_ACK
00000317 1106 ; JP C,EE_ERR
00000317 7bfe 1107 EE2 JR C,EE2 ; freeze for error
00000319 1108 ;
00000319 1109 ; read at current position
00000319 1110 ;
00000319 d60391 1111 PG_RD1 CALL START
0000031c 46eb01 1112 OR DEV_ADDR,#01H
0000031f 48eb 1113 LD DATA,DEV_ADDR
00000321 d60354 1114 CALL OUTBYT
00000324 d60369 1115 CALL REC_ACK
00000327 1116 ; JP C,EE_ERR
00000327 7bfe 1117 EE3 JR C,EE3 ; freeze for error
00000329 d6033f 1118 PG_RD2 CALL INBYT
0000032c f3a4 1119 LD @RAM_PTR, DATA
0000032e 00ec 1120 DEC BYTE_CNT
00000330 6b06 1121 JR Z,PG_RD3
00000332 d603b2 1122 CALL ACK
00000335 ae 1123 INC RAM_PTR
00000336 8bf1 1124 JR PG_RD2
00000338 1125 ;
00000338 d603b9 1126 PG_RD3 CALL NACK
0000033b d603a4 1127 CALL STOP
0000033e af 1128 RET
0000033f 1129 ;
0000033f 1130 ; input byte from i2c device
0000033f 1131 ;
0000033f 5f 1132 INBYT WDOG
00000340 46ef08 1133 OR OLD_P2M,SDA_HI
00000343 f9f6 1134 LD P2M,OLD_P2M
00000345 7c08 1135 LD BIT_CNT,#08H
00000347 d603c0 1136 IN_1 CALL CLOCK
0000034a 10e4 1137 RLC DATA
0000034c 7af9 1138 DJNZ BIT_CNT,IN_1
0000034e 56eff7 1139 AND OLD_P2M, SDA_LO
00000351 f9f6 1140 LD P2M,OLD_P2M
00000353 af 1141 RET
00000354 1142 ;
00000354 1143 ; output byte to i2c device
00000354 1144 ;
00000354 5f 1145 OUTBYT WDOG
00000355 7c08 1146 LD BIT_CNT,#08H
00000357 10e4 1147 OUT_1 RLC DATA
00000359 7b05 1148 JR C,OUT_2
0000035b 5602f7 1149 AND P2,SDA_LO
0000035e 8b03 1150 JR OUT_3
00000360 460208 1151 OUT_2 OR P2,SDA_HI
00000363 d603c0 1152 OUT_3 CALL CLOCK
00000366 7aef 1153 DJNZ BIT_CNT,OUT_1
00000368 af 1154 RET
00000369 1155 ;
00000369 1156 ; test for receice acknowledge
00000369 1157 ;
00000369 46ef08 1158 REC_ACK OR OLD_P2M,SDA_HI
0000036c f9f6 1159 LD P2M,OLD_P2M
0000036e 460208 1160 OR P2,SDA_HI
00000371 d603c0 1161 CALL CLOCK
00000374 56eff7 1162 AND OLD_P2M,SDA_LO
00000377 f9f6 1163 LD P2M,OLD_P2M
00000379 af 1164 RET
0000037a 1165 ;
0000037a 1166 ; poll i2c dev for ready condition
0000037a 1167 ;
0000037a 8c00 1168 WR_POLL LD ACK_CNT,#00H
0000037c 5f 1169 WR_POLL1 WDOG
0000037d 00e8 1170 DEC ACK_CNT
0000037f 6b0e 1171 JR Z,WR_POLL2
00000381 d60391 1172 CALL START
00000384 48eb 1173 LD DATA,DEV_ADDR
00000386 d60354 1174 CALL OUTBYT
00000389 d60369 1175 CALL REC_ACK
0000038c 7bee 1176 JR C,WR_POLL1
0000038e af 1177 RET
0000038f 1178 WR_POLL2 ; CALL START
0000038f 1179 ; CALL STOP
0000038f 1180 ; JP EE_ERR
0000038f 8bfe 1181 EE4 JR EE4 ; freeze for error
00000391 1182 ;
00000391 1183 ; issue a start command
00000391 1184 ;
00000391 460208 1185 START OR P2,SDA_HI
00000394 ff 1186 NOP
00000395 ff 1187 NOP
00000396 460210 1188 OR P2,SCLK_HI
00000399 ff 1189 NOP
0000039a ff 1190 NOP
0000039b 5602f7 1191 AND P2,SDA_LO
0000039e ff 1192 NOP
0000039f ff 1193 NOP
000003a0 5602ef 1194 AND P2,SCLK_LO
000003a3 af 1195 RET
000003a4 1196 ;
000003a4 1197 ; issue a stop command
000003a4 1198 ;
000003a4 5602f7 1199 STOP AND P2,SDA_LO
000003a7 ff 1200 NOP
000003a8 ff 1201 NOP
000003a9 460210 1202 OR P2,SCLK_HI
000003ac ff 1203 NOP
000003ad ff 1204 NOP
000003ae 460208 1205 OR P2,SDA_HI
000003b1 af 1206 RET
000003b2 1207 ;
000003b2 1208 ; issue a ack continue page
000003b2 1209 ;
000003b2 5602f7 1210 ACK AND P2,SDA_LO
000003b5 d603c0 1211 CALL CLOCK
000003b8 af 1212 RET
000003b9 1213 ;
000003b9 1214 ; issue a nack terminate page
000003b9 1215 ;
000003b9 460208 1216 NACK OR P2,SDA_HI
000003bc d603c0 1217 CALL CLOCK
000003bf af 1218 RET
000003c0 1219 ;
000003c0 1220 ; issue a clock pulse
000003c0 1221 ;
000003c0 460210 1222 CLOCK OR P2,SCLK_HI
000003c3 df 1223 SCF
000003c4 760208 1224 TM P2,SDA_HI
000003c7 eb01 1225 JR NZ,CLOCK_1
000003c9 cf 1226 RCF
000003ca 5602ef 1227 CLOCK_1 AND P2,SCLK_LO
000003cd af 1228 RET
000003ce 1229 ;
000003ce 1230 ; EE_ERR: JP EE_ERR
000003ce 1231 ;
000003ce 1232 ;
000003ce 2a205a3820436c6f 1233 .ascii "* Z8 Clock by "
000003d6 636b20627920
000003dc 58442e2028632920 1234 .ascii "XD. (c) 1997 - "
000003e4 31393937202d20
000003eb 7665722e20312e30 1235 .ascii "ver. 1.00 "
000003f3 3020
000003f5 7765313073657039 1236 .ascii "we10sep97"
000003fd 37
000003fe 1237 ; .byte 0FFH,0FFH
000003fe 202a 1238 .ascii " *"
00000400 1239
-
-
-
THINK MAN/WOMAN THINK BEFORE DO IT ...
-
