The Intel 8085A is a complete 8 bit parallel Central Processing Unit (CPU). Its instruction set is 100% software compatible with the 8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system speed.

Its high level of system integration allows a minimum system of three IC's (8085A (CPU), 8156 (RAM/IO) and 8355/8755A (ROM/PROM/IO) while maintaining total system expandability. The 8085A-2 is a faster version of the 8085A

The 8085 incorporates all of the features that the 8224 (clock generator) and 8228 (System controller) provede for the 8080A, Thereby offering a high level of system integration.

The 8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The on-chip address latches of 8155/8156/8755A memory products allow a direct interface with the 8085A.

Table 1. Pin Description

A8-A15	O	Address Bus: The most significan 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET
AD0-AD7	I/O	Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus furing the first clock cycle (T state) of a machine Cycle. It then becomes the data bus furing the second and third clock cycles.
ALE	O	Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge of ALE can also be used to strobe the status information. ALE is never 3-stated.
S0,S1 and IO/M	O	Machine Cycle Status:  IO/M  S1 S0  Status 0 0 1 Memory Write 0 1 0 Memory Read 1 0 1 I/O Write 1 1 0 I/O Read  0 1 1 Opcode fetch 1 1 1 Opcode fetch 1 1 1 Interrupt Acknlo. * 0 0 Halt * X X Hold * X X Reset * = 3-state (high impedance) X= unspecified S1 can be used as an advanced R/W status. IO/M, S0 and s1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines.
RD	O	Read Control:A low level on RD indicates the selected memory or I/O device is to be read and that the Data Bus is available for the ata transfer, 3-stated during Hold and Halt modes and during RESET.
WR	O	Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR. 3-stated during Hold and Halt modes and during RESET.
READY	I	Ready: If READY is high during a read or write cycle, it indicates that the momory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY to go high before completing the read or write cycle. READY must conform to specified setup and hold times.
HOLD	I	Hold: Indicates that another master is requesting the use of the address and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can ragain the bus only after the HOLD is remobed. When the HOLD is acknowledged, the Address, Data, RD, WR , and IO/M lines are 3-stated
HLDA	O	Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The Cpu tekes the bus one half clock cycle after HLDA goes low.
INTR	I	Interrupt request: Is used as a general purpose Interrupt. It is sampled only during the next to the last clock cycle of an instruction and during the next to the last clock cycle of an instrucion and during HOld and Halt states. IF it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routing. The INTR is enabled and disabled by software. It is isabled by Reset and immediately after an interrupt is accepted.
INTA	O	Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port.
RST 5.5 RST 6.5 RST 7.5	I	Restart Interrupts: These three intputs have the same timings as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in Table 2. These interrupts have a higher priority then INTR, In addition, they may be individually masked out using the SIM instruction.
TRAP	I	Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or RST5.5-7.5. It is unaffecte by any mask or interrupt Enable. It has the highest priority of any interrupt. (see Table 2.)
RESET IN	I	Reset In: Sets the Program Counter to zero and resets the interrupt Enable and HOLD flip-flops. The data and adress buses and the control lines are 3-stated during RESET and because of the asynchronous nature of RESET, the processor's internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as long as RESET IN is applied.
RESET OUT	O	Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods.
X1,X2	I	X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. X1 can also be an external clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal operating frequency.
CLK	O	Clock: Clock output for use as a system clock. The period of CLK is twice the X1,X2 input period.
SID	I	Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed
SOD	O	Serial Output Data Line: The putput SOD is set or reset as specified by the SIM instruction.
VCC		Power: +5 volt supply.
VSS		Ground: Reference

Table 2. Interrupt Priority, Restart Address, and Sensitivity

Name	Priority	Address Branched To (1) When Interrupt Occurs	Type Trigger
TRAP	1	24H	Rising edge AND high level until sampled.
RST 7.5	2	3CH	Rising edge (latched).
RST 6.5	3	34H	High level until sampled.
RST 5.5	4	2CH	High level until sampled.
INTR	5	See Note (2).	High level until sampled.

NOTES:
1. the processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.

FUNCTIONAL DESCRIPTION

The 8085A is a complete 8-bit parallel central processor. It is designed with N-channel depletion loads and requires a single +5 volt supply. Its basic clock speed is 3Mhz (8085A) or 5MHZ (8085A-2), thus improving on the present 8080A's performance with hight system speed. Also it is designed to fit into a minimum system of three IC's: The cpu (8085A), a RAM/IO (8156), and a ROM or EPROM /IO chip (8355 or 8755A).

The 8085A has twelve addressable 8-bit registers. our of them can funtion only as two 16-bit register pairs. Six other can be used interchangeably as a 8-bit register or a 16-bit register pairs. The 8085A register set is as follows:

Mnemonic	Register	Contents
ACC or A	Accumulator	8 bits
PC	Program Counter	16-bit address
BC, DE, HL	General-Purpose Registers; data pointer (HL)	8 bits x 6 or 16 bits x 3
SP	Stack Pointer	16-bit address
Flags or F	Flag Register	5 flags (8 bit space)

The 8085A uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data bus. These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the resto of the machine cycle the data bus is used for memory or I/O data.

The 8085A provides RW, WR S0, S1 and IO/M signals for bus contro. An interrupt acknowledge signale (INTA) is also provided. HOLD and all interrupts are synchronized with the processor's internal clock. The 8085A also provides serial Input Data (SID) and Serial Output Data (SOD) lines for simple serial interface.

In addition to these features, the 8085A has three maskable, vector interrupts pins and on nonmaskable TRAP interrupt.