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This is the list of patents issued by Giovanni Naso
· Giovanni Santin ; Giovanni Naso ; Sebastiano D'arrigo ; Michael Smayling
A FLASH EEPROM ARRAY
WITH SEPARATED P-TANK, INSULATED FROM THE SUBSTRATE BY A DEEP N-TANK
Abstract
: The use of a
separated p-tank, insulated from the substrate by a deep n-tank, permits to
pump a selected bit line of a flash EEPROM array to negative voltage. So the
value of the voltage to be applied to the word line during programming can be reduced
as well as the high voltage performance requirements on the process.
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·
Giovanni Santin ; Giovanni Naso.
ACTIVE SENSE AMPLIFIER
WITH DYNAMIC PRE-CHARGE TRANSISTOR
Abstract : A pre-charge
transistor is inserted in a classical sense amplifier schematics to actively
bypass a current mirror reducing time necessary to charge a bitline
and diminishing the probability of a read error being mirrored to the output
sense amplifier.
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· Giovanni Naso ; Giovanni Santin ; Sebastiano D'arrigo.
NEGATIVE VOLTAGE CHARGE
PUMP WITH FEEDBACK CONTROL
Abstract : A system to
generate a controlled ramp, to regulate the regime value and to trim this value
(programming EEPROM fuses) in a negative charge pump has been designed. In
previous schematics a negative charge pumps were not regulated in ramp and
amplitude nor trimmable thus having a risk to have
not adequate value of ramp and amplitude depending on the process spreads.
Furthermore the patented regulator allows to have a unique charge pump
schematics for different EEPROM array size.
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· Giovanni Naso ; Domenico Chindamo ; Robert Fleck ; Luat Pham ; Marco Mancinelli.
ROW AND COLUMN
REDUNDANCY FOR EMBEDDED SRAMs ORGANIZED BY SEGMENTS.
Abstract : A system to
replace failing rows and/or columns in embedded SRAM organized by segments has
been designed. With an area increase of 5% typical an yield increase between
35% and 15% was obtained.
TI number 23889 - Approved
in
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· Giovanni Santin ; Giovanni Naso
FLASH CELL FUSE CIRCUIT
Abstract : A circuit based
on flash cells is used to store information to configure a memory chip; to trim
analog voltage inside a memory chip; to store address of failing row and column
to be replaced by redundant rows and columns in a memory chip. The circuit is
organized according to the same array structure of the flash memory core where
it is used and its operations (program-erase-read) are based on the same
structures used for regular memory cells.
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· Giovanni Naso ; Giovanni Santin ; Pasquale Pistilli
FLASH MEMORY SECTOR
TAGGING FOR CONSECUTIVE SECTOR ERASE OR BANK ERASE
Abstract : each sector of a
FLASH memory is provided with a tagging circuit. Once one or more sectors are
tagged they can be erased one after the other with a single user/test command
using internal voltages or they can be erased all together with a single
user/test command eventually using external voltages.
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· Giovanni Naso ; Elio D'Ambrosio
TEST MODE DECODER IN A FLASH MEMORY
Abstract : This patent
describes a compact and versatile interface and decoder to put an integrated
circuit into test mode.
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· Girolamo Gallo ; Giuliano Gennaro Imondi ; Giovanni Naso ; Tommaso Vali
DUAL BUS MEMORY BURST
ARCHITECTURE
Abstract : This patent
describes a method and apparatus for a memory device including a burst
architecture employing a bus architecture that is multiplexed onto an output
bus at a clock rate that is doubled. The resulting architecture effectively
doubles throughput without increasing memory device latency.
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· Giovanni Naso ; Pietro Piersimoni ; Tommaso Vali
CHIP PROTECTION REGISTER
UNLOCKING
Abstract : This patent
describes a protection register lock bit erase enable circuit for FLASH
memories. The lock bit can be erased/programmed in factory in wafer form for
multiple program/erase of protection register. The lock bit is not accessible
in packaged form and for this reason the user cannot perform multiple
program/erase operations of the protection register.
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· Giovanni Naso ; Pasquale Pistilli ; Luca De Santis ; Pasquale Conenna
ROM-BASED CONTROLLER MONITOR
IN A MEMORY DEVICE
Abstract :Erase and program
operations in FLASH memories are accomplished using complex algorithms composed
of many different steps and requiring control actions over timing, counters and
analog voltages. Word program is typically a loop of program pulses and program
verify until the right value is written with appropriate margin. Sector erase
is typically a sequence of steps: pre-program of all words in the sector,
pre-program verify, erase, erase verify, depletion check, depletion recovery. A
circuit called algorithm controller is designed in order to manage the
execution of different steps in the erase and program algorithms. Furthermore
the erase and program operations in a sector can be suspended to start a read
operation in another sector and the algorithm controller must correctly manage
the suspension and its resume. Once an erase/program operation has been
requested, and the algorithm is started, it is not possible to say which
particular step the algorithm controller is performing at a particular time. In
fact the erase and program algorithms are adaptive and a step is started only
when conditions associated to the previous step are satisfied. A way to monitor
the very basic activity of an algorithm controller is the status register
concept which has been widely used in FLASH design and is available to the end
user to interface the FLASH chip with the board controller. Besides the status
register technique, in a new concept of a programmable- ROM-based algorithm
controller, the activity during erase and program algorithm can be carefully
monitored using test modes. A first test mode called "external clock
force" (tck) allows to override the internal
algorithm controller clock using a clock applied to an external pad thus imposing
a specific clock period and synchronization to the algorithm controller. A
second test mode called "ROM address monitor" (tra)
allows to follow the evolution of the algorithm reading ROM address to the
upper part of the output pads while status register information is still
available on the lower part of the output pads. A third test mode called
"write state machine monitor" (twsm) allows
to monitor on output pads rom addresses and different
control/operand data that can be selected using external address pads.
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· Girolamo Gallo ; Giulio Marotta ; Giovanni Naso
OUTPUT BUFFER STRENGTH
TRIMMING
Abstract :The output buffer
of an integrated circuit must be sized large enough to provide sufficient
sinking and sourcing to the load and transmit a signal within a short time.
Unfortunately this requirement can demand a high rate of change in the current
and can cause significant noise due to power line voltage drop and/or ground
line voltage bump. This noise can upset nominal operation of the chip’s
circuits that share the power/ground bus with the output buffers. In modern
applications, where integrated circuits are assembled in very small printed
circuit boards (PCB) with optimized routing, the load that an integrated
circuit has to drive can be much smaller than the load used as reference to
design the output driver size. In this case an internal (volatile or non
volatile) trimming of the output buffer size can be set up in order to minimize
noise while achieving good output rise/fall performances.
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· Maurizio Di Zenzo ; Maria Luisa Gallese ; Giuliano Gennaro Imondi ; Giovanni Naso
BACKGROUND BLOCK ERASE
CHECK FOR FLASH MEMORIES
Abstract :Erasing a Flash
memory with a given margin vs data gain requires a
complex internal algorithm. It is possible to erase the memory without making
use of the internal algorithm, just using a simplified external erase algorithm
with parameters specified by the Flash manufacturer. This is what is normally
done by Flash manufacturers. The external algorithm does not perform complex
cycles, thus avoiding to increase considerably the testing time. In most cases,
the external algorithm used at final test is sufficient for a good erase.
However, few cells in some memory chip may be more sensitive to data gain. With
the external algorithm, it is not guaranteed that 100% of the chips are erased
with safety margin vs the data gain that can be
expected after a period of storage of the chip, elapsing form the end of the
final test in the manufacturer’s house until the first use in the production
line by the customer. If the customer assumes the chip is erased but it is not,
the code put into the Flash will be wrong. This could generate problems in the
customer’s production line. The customers would prefer to operate first an
erase verify with a given margin on all memory chips before using them in the
production line. But the customer should spend the testing time for an erase
check with safety margins on all incoming memory chips and does not want to
bear the associated cost. The purpose of the present invention is to provide an
on-chip method to perform the erase check of each single block of the Flash memory
with a known margin against data gain, with virtually no time loss on the test
equipment. The customer, before any writing of application data into the
memory, must only send a (new) Block Erase Check user command to the Flash to
perform the erase check, selecting a margin to be checked versus data gain.
Then the chip will proceed in background to perform the erase check. This
operation is quite fast by itself (0.5 seconds for a 32M Flash) and leaves the
microprocessor controlling the testing equipment free for other activities.
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· Giovanni Naso ;Pietro Piersimoni ; Tommaso Vali
CHIP PROTECTION REGISTER
UNLOCKING
Abstract : An improved
Flash memory device is described with a protection register lock bit erase
enable circuit. A bond pad coupled to the lock bit erase enable circuit of the
improved Flash memory is not bonded when the individual Flash memory chip wafer
is packaged. This allows the memory manufacturer to access the bond pad and
erase the lock bits while the chip is still in wafer form via a test probe
card, but makes the lock bits effectively unreasonable when the chip wafer is
packaged. This enables the memory chip manufacturer to enhance reliability and
fault tolerance of the Flash memory device by thoroughly testing the lock bits
and protection register functionality. Additionally, the lock bit erase enable
circuit increases manufacturing flexibility by allowing the memory chip
manufacturer to reprogram the protection register and lock bits in case of
organizational changes or inadvertent or erroneous programming of the
protection register.
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·
Giovanni Naso
DATA COMPRESSION READ
MODE FOR MEMORY TESTING
Abstract : A method to
efficiently compress information related to memory testing failing bits into a
limited amount of IOs.
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·
Giovanni Naso
MULTIPLE LEVEL DATA
COMPRESSION READ MODE FOR MEMORY TESTING
Abstract : A method to
efficiently compress information related to memory testing failing bits into a
limited amount of IOs.
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·
Giovanni Naso ; Stefano Donnola
FILTERED REGISTER
ARCHITECTURE TO GENERATE ACTUATOR SIGNALS
Abstract : Register architecture can generate actuator
signals under controller operation (user mode) or under tester operation (test
mode). Prior art does not allow to perform user mode algorithm keeping actuator
signals previously set in test mode. Present invention improves the prior art
introducing a filter structure able to perform user mode algo
while keeping the actuators previously set in test mode.
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Number : U.S. 8275926 – Issued : Sept 25,2012
·
Giovanni Naso ; Stefano Donnola
FUSE DATA ACQUISITION
Abstract
: The patent is related to safe a way to
download at power-up content of fuses stored in a mini-array. A specific fuse
having low VT is used as an enabler to download the other regular fuses.
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* Last update: Jan 10, 2013 *