Welcome !
This is the list
of articles written by Giovanni Naso
Sometimes I had the opportunity to write technical
articles in the field of my activity and they are listed
below:
1. M.Gill ; R.Cleavelin ; S.Lin ; M.Middendorf ; A.Nguyen ; J.Wong ; B.Huber ;S.D'Arrigo ; P.Shah ; E.Kougianos ; G.Santin ; G.Naso
A NOVEL SUBLITHOGRAPHIC TUNNEL-DIODE-BASED 5V-ONLY
FLASH MEMORY
TI Technical Journal Vol.8 ,
N.2 - March/April 1991
Electron Devices Meeting, 1990. Technical Digest.,
International , 9-12 Dec. 1990 Pages:119 - 122
2. E.D'Ambrosio ;
M.Fragano ; G.Imondi ; M.Lanciano ; S.Menichelli ; G.Naso
A 2.9 MEGABIT FIELD MEMORY ESPECIALLY SUITABLE FOR PAL
plus APPLICATIONS
Texas Instruments Asia Pacific
Technical Conference - June 1994
3. E.D'Ambrosio ;
M.Fragano ; G.Imondi ; M.Lanciano ; S.Menichelli ; G.Naso
A 2.9 MEGABIT FIELD MEMORY FOR IDTV AND PAL+ APPLICATIONS
ICCE - International Conference on Consumer
Electronics - June 1994
4. E.D'Ambrosio ;
M.Fragano ; G.Imondi ; M.Lanciano ; S.Menichelli ; G.Naso
A 2.9 MEGABIT FIELD MEMORY ESPECIALLY SUITABLE FOR PAL plus
APPLICATIONS
IEEE Transaction on Consumer electronics Vol.40 , N.3 - August 1994
5. G.Naso ; E.D'Ambrosio ; P.Pistilli ; C.Palazzo
DESIGN FOR TESTABILITY IN TMS4C2972/3
Texas Instruments Asia Pacific
Technical Conference - September 1995
6. E.D'Ambrosio ;
G.Imondi ; S.Menichelli ; G.Naso ; P.Pistilli ; U.Skowronek
LA MEMORIA DI QUADRO: UN CHIP DERIVATO DALLA MEMORIA 16 MBIT
DRAM STANDARD
Published in Italian in Alta Frequenza. Vol.9 N.2
Marzo-Aprile 1997 p.22-26
7. D.Chindamo ;
M.Mancinelli ; G.Naso ; G.Porrovecchio
MODULI DI MEMORIA SRAM PER DSP E MICROCONTROLLORI
Published in Italian in Alta Frequenza. Vol.9 N.2
Marzo-Aprile 1997 p.48-54
8. H.Takahashi ;
S.Abiko ; S.Mizushima ; Y.Hozawa ; K.Tashiro ;S.Muramatsu ; M.Fusumada ; A.Todoroki ; Y.Tanaka ; M.Itoigawa ; I.Morioka ; H.Mizuno ; M.Kojima ; G.Naso ; E.Ego ; F.Chirat
A 100 MIPS HIGH SPEED AND LOW POWER DIGITAL SIGNAL PROCESSOR
IEICE Transaction on Electronics. Vol. E80-C. NO. 12 December 1997 p.1546-1552
9. G. Marotta; A. Macerola; A. D’Alessandro; A. Torsi; C. Cerafogli;
C. Lattaro; C. Musilli; D. Rivers; E. Sirizotti; F. Paolini; G. Imondi;
G. Naso; G. Santin; L. Botticchio; L. De Santis; L. Pilolli; M.L. Gallese;
M. Incarnati; M. Tiburzi; P. Conenna; S. Perugini; V. Moschiano;
W. Di Francesco; M. Goldman; C. Haid; D. Di Cicco; D.
Orlandi; F. Rori; M. Rossini; T. Vali; R. Ghodsi; F. Roohparvar
A 3BIT/CELL 32Gb NAND FLASH MEMORY AT 34 nm WITH 6MB/S
PROGRAM THROUGHPUT AND WITH DYNAMIC 2BIT/CELL BLOCK CONFIGURATION MODE FOR A PROGRAM
THROUGHPUT INCREASE UP TO 13MB/S
ISSCC2010 – International Solid State Circuit
Conference – San Francisco 2010
10. M Goldman; K.
Pangal; G. Naso; A. Goda
25nm 64Gb 130mm2 3bpc NAND Flash
Memory
International Memory Workshop, IMW 2011
11. G. Naso; L. Botticchio; M. Castelli; C. Ceratogli; M. Cichocki; P. Cotenna; A. D’Alessandro; L. De Santis; D. Di Cicco; W. Di Francesco; M.L. Gallese; G.
Gallo; M. Incarnati; C. Lattaio; A. Macerala; G. Marotta; V. Moschiano; D.
Orlandi; F. Paolini; S. Perugini; L. Pilolli; P.
Pistilli; G. Rizzo; F. Rori; M. Rossini; G. Santin; E. Sirizotti;
A. Smaniotto; U. Siciliani; M. Tiburzi; R. Meyer; A. Goda; B. Filipiak; T.
Vali; M. Helm; R. Ghodsi
A 128Gb 3b/cell NAND Flash
Design Using 20nm Planar-Cell Technology
ISSCC2013
– International Solid State Circuit Conference – San Francisco
2013
12. Giovanni
Naso, Senior Design Manager-NVE DE; Marco
Carminati, SMTS-NVE DE; Carmelo
Condemi, Senior Design Manager-NVE DE;
Luca De Santis, DMTS-NVE DE; Walter Di Francesco, DMTS-NVE DE; Cristina Lattaro, Senior CAD Manager-NVE DE; Agostino Macerola, SMTS-NVE
DE; Giulio Giuseppe Marotta, DMTS-NVE
DE; Violante Moschiano, DMTS-NVE
DE; Luigi Pilolli, Principal Design Engineer-NVE
DE; Massimo Rossini, Senior
Design Manager-NVE DE; Giovanni Santin, DMTS-NVE DE; Umberto Siciliani, Senior Design Manager-NVE DE; Stefano Spagliccia,
Senior Layout Manager-NVE DE; Berardino
Tronca, Senior Layout Manager-NVE DE; Andrea
Xotta, Principal Design
Engineer-NVE DE; Ali Mohammadzadeh,
Senior Design Manager-NVE DE; Qiang Tang, Director-NVE DE; Tommaso Vali, Senior Director-NVE
DE Europe; and Ramin Ghodsi,
Vice President-DE
& NVE
1Tb density,
4 bits-per-cell 3D NAND flash in 110s technology
Micron TLP - 2017
* Last update: September 2020 *