Guide of FAULT TOLERANT DESIGN
Adrian Thompson's Hardware Evolution Page.
Adrian Thompson does Research on Evolvable Hardware.
I'm mainly interested in the use of `soft' computing techniques, such as neural networks and genetic algorithms, in engineering design
The main focus of this has been evolutionary algorithms to design microelectronic circuits and, more recently, nano-electronics
Evolutionary Electronics is the use of evolutionary algorithms in the design of electronic systems
There are many potential applications for evolutionary algorithms in electronics, such as optimisation of parameter values or component placement & routing, test pattern generation, and even in the design process itself
The focus of my own work has been to ask 'What can evolutionary design do that conventional methods can't?' rather than trying to compete with conventional design or automate it
Publications Keywords: Evolutionary electronics, evolutionary robotics, single-electron circuit design, fault tolerance, physics of computation, artificial evolution, evolutionary computation, genetic algorithms ( GA ), artificial life ( ALife ), design automation
Hardware Evolution: Automatic design of electronic circuits in reconfigurable hardware by artificial evolution
Intel iAPX 432 - Wikipedia, the free encyclopedia
Growing article, with links to many related topics. [Wikipedia]
The Intel iAPX 432 was 's first design, introduced in 1981 as a set of three
The iAPX 432 was intended to be Intel's major design for the 1980s, implementing many advanced and features in hardware, which led them to refer to the design as the Micromainframe
However, the design was extremely complex compared to the mainstream microprocessors of the era, so much so that Intel's engineers weren't able to translate the design into an efficient implementation using the semiconductor technology of its day
The design was intended to be purely 32-bit from the outset, and be the backbone of Intel's processor offerings in the 1980s
However the design was well beyond the capabilities of the existing of the era, and had to be split into several individual chips
The core of the design was the two-chip General Data Processor ( GDP ) which was the main processor
The two-chip GDP had a combined count of approxmately 97, 000, which the single chip IP had approximately 49, 000, making them some of the largest IC designs of the era
[] The project's failures Several design features of the iAPX 432 conspired to make it much slower than it could have been
Distributed Systems Research Group - Overview
Research focus includes distributed operating systems and distributed system
management. Projects include Arjuna and Voltan.
Byzantine Fault Tolerance: In mission-critical applications, it is prudent to design and implement systems under a highly unrestricted fault assumption, namely, that a failed processor and its processes, in principle, can behave in a fail-uncontrolled manner (in the literature this failure mode is often referred to as the Byzantine failure mode)
We designed, implemented and patented Byzantine fault tolerant processing elements (Voltan failure masking and fail-silent processes) that used novel replicated processing techniques and algorithms [, ]
Since then we have redesigned the system for the world of Web services and Grid computing as a tool for service composition and enactment []
Fault Tolerance and Distributed Computing Technology
Fault tolerant Microsoft, UNIX and Oracle server solutions and firewall/VPN
appliances. Remote monitoring, management, data storage, backup and disaster ...
· · · · · High Availability, Fault Tolerance, Computer Forensics What does downtime cost your business? How do lost productivity and lost transactions affect your relationship with your customers? What level of availability - high or assured - do you need for your mission-critical application or business-critical services? Whether you're running Windows or Linux, will work with you to design the right fault tolerance technology solution
info: FAULT TOLERANT DESIGN
Photo by www.stratus.com
Yield and Reliability of VLSI Circuits
Researching yield models and their verification, yield analysis and estimation
techniques, yield enhancement schemes, and reliability and parametric yield.
Pradhan, 'Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay, ' IEEE Journal of Solid-state Circuits, Vol
of the International Symposium on Quality of Electronic Design (ISQED'02), pp
of the International Symposium on Quality of Electronic Design, pp
Koren, ``Should Yield be a Design Objective?' (invited paper), Proc
of the International Symposium on Quality of Electronic Design, pp
of the 5th ACM/SIGDA Physical Design Workshop , pp
Koren, 'Yield Enhancement Designs for WSI Cube Connected Cycles, ' Proc
Pradhan, 'Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement, ' Proc
Quantum Go
A tool to teach principles of Fault-Tolerant Design, based on the game of go.
David Nicol presents his latest weird idea: Quantum Go A tool to teach principles of Fault-Tolerant Design, based on the ancient Chinese game of Wei-Chi, also known as Go or Baduk
How does all this relate to Fault-Tolerant Design? The mutation phase represents faults
It is my belief that Quantum Go provides a conceptual framework for designing fault-tolerant systems, as go-stone structures able to remain on the board even with mutations happening must tolerate, or co-exist with, faults, or situations which do not occur in normal 'faultless' Go
ORNL CUMULVS Project
A software infrastructure for the development of collaborative environments.
The site includes downloads, papers, and links to related projects.
Through the use of interaction, the computer will become a more useful tool to the engineer, allowing experimentation and real time exploration of a design space
FT Languages Home Page
Fault-tolerant projects, goal: enhance language support for distributed programs
with FT needs, most high-level languages lack good support for such, ...
FT-SR is unique in that it has been designed to support equally well any of the programming paradigms that have been developed for fault-tolerant distributed systems, including the object/action model, the restartable action paradigm, and the replicated state machine approach
To do this, the language is designed to support the implementation of systems modeled as collections of fail-stop atomic objects
The system design is based on using ordered atomic multicast in the runtime system, a strategy that allows efficient implementation of stable tuple spaces as replicated state machines
Benefits
Photo by www.ciss.dk
FTRTFT'02 - Welcome! 7th International Symposium on Formal Techniques in Real-Time and
Fault Tolerant
Systems. University of Oldenburg, Germany; 9--12 September 2002.
If you are still interested but can not get the frameset please contact The Symposium will present advances in the development and use of formal techniques in the design of real-time, hybrid, fault-tolerant embedded systems, covering all stages from requirements analysis to hardware and/or software implementation
Topics within the theme of this Symposium include requirements' capture safety analysis formal models specification verification testing timing estimation partitioning schedulability analysis hardware/software codesign fault tolerance real-time communications services component-based design formal models of object-oriented design secure global and mobile computing
Sensei: overview
Sensei is a project supporting the development of fault tolerant applications
using active replication. Its interface is specified in CORBA and JavaRMI, ...
Using the replicated components, and the given support, it is possible to design replicated applications as if they were just multithread
The components under study are containers and, in fact, the design is based on the java.util package found in Java2
The purpose of this subsystem is to leverage the replicated application of designing its own components
This site provides the following information: : this page : General issues concerning the design of the overall system
: design and implementation of the reliable group communication layer
: Methodology used, and design and implementation of this layer, which features the components support
Kane Kim
University of California, Irvine - Real time systems, distributed computing,
fault tolerant systems.
Fellow of the SPDS (Society for Process and Design Science) elected in June 2000 Served as General Chairman and Program Chairman of 5 International Conferences sponsored by the IEEE Computer Society
President-Elect (for 07/2004 06/2005 and slated to serve as 34th President during 07/2005 06/2006), (Former elected VP, former elected Auditor, and former elected Councilor representing Group L (Computer Science and System Engineering)) of KSEA (Korean-American Scientists & Engineers Association) Research Accomplishments Originated the DRB technique and several other widely applicable basic approaches for cost-effective design of ultra-reliable fault-tolerant, real-time, distributed and parallel computer systems
Throwing Destructors
It is becoming increasingly popular to consider throwing destructors a bad practice.
This document presents some insights on the problem and shows that maybe ...
FAULT TOLERANT DESIGN ?
Application Development Trends - The CORBA State of the union
Article provides information on the background to CORBA, where CORBA can be found
today and standards activities. By Charlotte Wales, Fred Waskiewicz.
Modeling of Power Consumption and Fault Tolerance for Electronic ...
Master of Science thesis focused on research aimed at creating simulation models
for power consumption and fault behaviour of electronic textile applications, ...
Intelligent Systems Research
Involves faculty and students in the Engineering Science department. Overview,
projects, publications, researchers, facilities and collaborations.
Research also is focused on large scale and decentralized control, optimal control, and fault tolerant control system design
A variety of questions dealing with the state/output feedback design of optimal controllers with pole placement and weight selection capabilities is being investigated
A second area is that of fault-tolerant control system design for applications where continuous and safe operation of the system under control is important for safety or economic reasons
Use of colour to visualize shape information Existing CAD systems are effective only at the lowest levels of design
The next generation of systems must, by contrast, provide help with design synthesis and analysis
To achieve this, several lines of research are being pursued, including the logical and psychological nature of the design task, and the behaviour of expert and novice designers
Prototype knowledge bases to support mechanical and architectural design are being developed, using an expert system shell with constraint propagation capabilities
Bayesian probabilistic reasoning in design Explanation and the human/computer interface Explanation in knowledge-based design Knowledge bases to support design reasoning Mixed-initiative systems Research in this area explores the use of model-based reasoning for design and diagnose faults
Excerpts from Butler Lampson's "Hints for Computer System Design"
Principle table and slogan outline explanation.
Excerpts from Butler Lampson's 'Hints for Computer System Design' The full document is now online as on Butler Lampson's page
1999.Mar.03 This page contains some excerpts from Butler Lampson's 'Hints for Computer System Design'
Lampson Hints for Computer System Design Ninth ACM Symposium on Operating Systems Principles in Operating Systems Review 17, 5 (October 1983) pages 33-48
From this experience come some general hints for designing successful systems
I claim no originality for them; most are part of the folk wisdom of experienced designers
Conclusion @ARTICLE{ LampsonHints83, author = 'Lampson, Butler W.', title = 'Hints for Computer System Design', journal = 'Operating Systems Review', publisher = 'ACM', year = 1983, month = October, volume = 17, number = 5, pages = 33-48, note = '{em Ninth ACM Symposium on Operating Systems Principles}
Later republished, but with less satisfactory copy editing, in {em IEEE Software} 1, 1 (January 1984) pages 11-28.' } @ARTICLE{ LampsonHints84, author = 'Lampson, Butler W.', title = 'Hints for Computer System Design', journal = 'IEEE Software', year = 1984, month = January, volume = 1, number = 1, pages = 11-28, note = 'This is republished, with less satisfactory copy editing, from {em Ninth ACM Symposium on Operating Systems Principles} in {em Operating Systems Review} 17, 5 (October 1983) pages 33-48.' } Comments encouraged
http://klabs.org : NASA Office of Logic Design - A scientific ...
Dedicated to the design and use of programmable and quick-turn technologies for
space flight applications.
Use a small number of good people." Kelly Johnson in Skunk Works by Ben Rich and Leo Janis Selected Papers John Rushby George Low, NASA MSC Office of Logic Design Seminars and Workshops : (May 9: RTAX-S Boot Camp; May 10: Briefing; May 11: Eclipse Boot Camp)
- All proceedings on-line (old page and most devices tested aren't here :-) : Military & Aerospace Programmable Logic User's Group XL - NEW!! - Home Page Archives Web Grunt: Richard Katz Last Revised May 26, 2006 NASA Office of Logic Design A scientific study of the problems of digital engineering for space flight systems, with a view to their practical solution
Internetwork Design Guide
This publication provides internetworking design and implementation information
and helps you identify and implement practical internetworking strategies that ...
Internetwork Design Guide All contents are copyright © 1992--2006 Cisco Systems, Inc
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